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Network Programs in the Fast Lane: Research Enabled by High-Throughput Programmable Switches

Traditionally, the packet processing logic of high-speed networking devices was fixed-function, defined during the chip manufacturing process. This limitation led to years-long innovation cycles to introduce non-standard behaviors in the network forwarding plane. However, the emergence of high-throughput programmable switching chips, such as Intel’s Tofino, over the last decade has sparked unprecedented speed in network innovation. The ability to dynamically reconfigure packet processing functionality in these switching chips allows for quicker implementation and deployment of “smarter” network programs within our networks’ forwarding plane. This technological advancement opens up avenues for addressing longstanding networking challenges as well as realizing future networks. In this talk, I will illustrate these opportunities by presenting two systems, FlowLens and Peregrine, along with a funded project, Myriarch, based on my research over the last five years.